1. Field of the Invention
The present invention relates to an image or video signal outputting apparatus. More specifically, the present invention relates to a video signal outputting apparatus which outputs N kinds of video signals to N of display means, respectively, like a time laps VCR.
2. Description of the Prior Art
One example of conventional such a kind of video signal outputting apparatus 1 applied for a time lapse VCR which outputs 4 kinds of video signals from a monitor by dividing a screen into 4 blocks is shown in FIG. 38. In this video signal outputting apparatus 1, video signals Y1 and Y3 outputted from an A/D converter 2a are written into a VRAM 4a in response to a write control signal from a microcomputer 3, and video signals Y2 and Y4 outputted from an A/D converter 2b are written into a VRAM 4b by the write control signal from the microcomputer 3. More specifically, the video signals Y1 and Y3 are written into areas A1 and A3 of the VRAM 4a shown in FIG. 39, respectively, and the video signals Y2 and Y4 are written into areas A2 and A4 of the VRAM 4b, respectively. Then, addresses of the VRAM 4a and 4b are scanned downward as shown in FIG. 40 such that the video signals Y1 to Y4 are read-out and outputted through a multiplexer 5 and a D/A converter 6. Therefore, images according to the video signal Y1 to Y4 are displayed on a monitor 7 as shown in FIG. 41.
Furthermore, in another example of conventional such a kind of video signal outputting apparatus 1 as shown in FIG. 42, video signals Y1 to Y4 outputted from an A/D converter 2a are sequentially written into areas A1 to A4 of VRAMs 4a and 4b, and video signals Y1 to Y4 outputted from an A/D converter 2b are sequentially written into areas B1 to B4 of VRAMs 4c and 4d. Since a microcomputer 3 switches write signals for the VRAMs 4a and 4b and write signals for the VRAMs 4c and 4d at every one field, video signals Y1-1 to Y4-1 outputted at a last time are written into the VRAMs 4a and 4b, and video signals Y1-2 to Y4-2 outputted at a present time are written into the VRAMs 4c and 4d, as shown in FIG. 43(B). Furthermore, a video signal Y1-3 outputted at a next time from the A/D converter 2a is written into the area A1 as shown in FIG. 43(C).
Thus, a newest video signal out of the video signals written into the VRAMs 4a to 4d is applied to a monitor 7. Accordingly, when the video signals are stored in the VRAMs 4a to 4d as shown in FIG. 43(B), images according to the video signals Y1-2 to Y4-2 in the VRAMs 4c and 4d are displayed on the monitor 7 as shown in FIG. 44(A). Then, during a time that an video signal Y1-3 is being written as shown in FIG. 43(C), the images shown in FIG. 44(A) are displayed on the monitor 7, and when writing of the video signal Y1-3 is completed, images according to the video signals Y1-3, Y2-2, Y3-2 and Y4-2 are displayed as shown in FIG. 44(B).
However, in the prior art shown in FIG. 38, a writing speed and a reading speed of the video signal are different from each other as shown in FIG. 45. Accordingly, in a case where reading is started while the video signal Y3-2 is being written in the area A3 as shown in, for example, FIG. 46, the last video signal Y3-1 and the present video signal Y3-2 are outputted on the monitor 7 as shown in FIG. 47, and therefore, there was a problem that the images are incoincident with each other at an upper side and a lower side of the monitor.
Further more, in the prior art shown in FIG. 42, though the problem that the images are incoincident with each other at the upper side and the lower side is solved, VRAMs twice the prior art shown in FIG. 38 are needed, and therefore, there was a problem that the number of parts increases and a cost becomes high.